EDA News Monday April 14, 2003 From: EDAToolsCafe _____ _____ About This Issue More M&A in EDA Cadence buys Get2Chip _____ April 14 - April 21, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Here's the press release, somewhat abridged: Cadence Design Systems, Inc. announced April 10th that the company has signed a definitive agreement to acquire Get2Chip. Cadence plans to integrate Get2Chip's technology into the Cadence Encounter platform for digital IC design. Get2Chip says that its patented core technology, called "global focused synthesis," provides "the industry's highest synthesis capacity and performance" for logic and interconnect structures for nanometer-scale physical design. Both companies say the Get2Chip technology complements the existing Cadence synthesis solution. Ray Bingham, President and CEO of Cadence, said: "Major customers have enthusiastically embraced the Get2Chip product. I am personally delighted to bring such an outstanding technology team into Cadence." Bernd U. Braune, Get2Chip's Chairman and CEO, said: "Get2Chip has demonstrated the impact of next-generation synthesis technology on nanometer designs. We have already enabled multiple designs of over 50 million gates with less effort and less cost. My whole team is excited about the synergy between Get2Chip and Cadence SoC Encounter." Ping Chao, Cadence Senior Vice President and General Manager, said: "With Get2Chip, Cadence plans to further demonstrate its unique ability to integrate our own technology with acquired technology from the industry's best and brightest. We continue to deliver on our commitment to provide customers with the best design solution. Get2Chip's extremely advanced nanometer-scale synthesis technology will strengthen the Cadence IC Digital design flow. This will go far to address our customers' demands for a high-end synthesis solution able to meet the challenges of designs at 90 nanometers and below." Cadence plans to retain most of Get2Chip's employees and will continue to support all of Get2Chip's customers and products. Cadence comments on the acquisition Meanwhile, in a brief 10-minute phone call with Penny Herscher, Executive Vice President of Cadence, it's clear that Cadence and Get2Chip are fully committed to this acquisition - and that everybody on both teams is also committed to staying "on message" about the when, where, and why of it all. Herschers' comments in brief: Q: Have you been busy answering phone calls and requests for interviews? A: We've been very busy this week talking to customers, investors, and the press. We're getting a very positive response from the customers. Q: How has Cadence stock reacted to the news? A: We're in a quiet period. I can't respond to that. Q: How many employees are there at Get2Chip and how many will be brought over to Cadence? A: About 50. We'll be bringing in almost all of them. Q: Is this acquisition intended for Cadence to own the complete flow? A: Not really. This is a continuation of a strategy that we've been pursuing for a couple of years. We're bringing the best technology together to provided a solution for customers to be productive across the whole flow. It's our intention to acquire young companies in ascendancy with young technology, and to integrate that technology into our tools. Q: Does this acquisition disrupt other synthesis initiatives at Cadence? A: No. We see the Get2Chip technology as complementary to our other initiatives. The Get2Chip technology is aimed at high-end, power users. Q: Does the Get2Chip acquisition intend to present direct, head-on competition to Synopsys as has been the Get2Chip message for several years? A: Our focus is not on competition. Our focus is on making our customers successful. This acquisition will improve success for our customers. Q: Is the industry anxious to have an alternative synthesis tool provider? A: Customers always welcome alternatives, in general. But customers always want the best technology. Q: Why now for the Get2Chip acquisition? Why not 6 months ago or 6 months from now? A: This was the right time for the acquisition as it fits in with the current momentum for the [Cadence] Encounter product. Q: How long has this acquisition been in the works? A: [A resounding chuckle] Q: How will the Get2Chip team be utilized at Cadence? A: Get2Chip President Chi-Ping Hsu will manage all synthesis initiatives at Cadence. Get2ChipChairman and CEO Bernd Braun will report directly to Ray Bingham as advisor to get the team integrated in. Vice President of Marketing Steve Carlson will stay with Chi-Ping Hsu. Q: Does Cadence have internal, proprietary procedures for smoothing the acquisition process? A: We do indeed have documentation to guide us through incorporating a new technology into our infrastructure. That's part of our core competency. Q: Who will be buying the drinks next week when the deal is finalized? A: Cadence will be buying the champagne. Industry News - Tools & IP Analog Design Automation, Inc. (ADA) announced that it has licensed SpaceCruiser client/server software from Oridus, Inc. The companies say that the SpaceCruiser software "gives ADA the ability to offer real-time desktop sharing via a fast and secure Web link." Aptix Corp. introduced its Flexible Prototyping Modules (FPM) with Xilinx XC2V8000 Virtex-II Platform FPGAs for use with the company's System Explorer and Software Integration Station systems. The company says that the FPMs enhance the system-level modeling capability of the Aptix platform and that developers can now use the I/O and IP capabilities, "as well as the higher speed and greater gate capacity of the Virtex-II Platform FPGAs from Xilinx." An FPM contains one or two Xilinx XC2V6000 or XC2V8000 Virtex-II FPGA ICs, and up to ten of the modules can be plugged directly into the Aptix System Explorer and/or Software Integration Station, to yield a maximum of 10+ million ASIC gates when using the dual-density XC2V8000 configuration. The FPMs are also compatible with Aptix systems software. Camstar announced a new release of InSite, software to improve data integration, manufacturing "responsiveness" and web services. InSite 3.2 extends the use of XML as a native transport format to include industry-standard Web services interfaces. These interfaces allow manufacturing and performance data to flow in real-time between InSite and other enterprise applications without the development of proprietary application links. Emulation and Verification Engineering (EVE) announced that it has raised $3.2 million in Series A Funding. The company says the funding will be used as working capital to build its R&D team, as well as for further expansion of worldwide marketing, sales and support structures. Investors, who each contributed one third of the funding, include 3i, Credit Lyonnais Private Equity (the Private Equity asset management company of the French bank Credit Lyonnais), and Siparex, an independent French VC. Esterel Technologies announced that its SCADE Suite is being used by Airbus' Flying Command Specification and Development group to design and verify the Airbus A380 flying commands. The company says that Airbus will also use SCADE to develop other electronic systems on the aircraft, including the braking and steering, cockpit display, flight warning, engine control, and air control systems. SCADE is a software product used to create a formal specification from which the user can automatically generate embeddable software code. Giga Solution, Mentor Graphics Corp., and UMC announced the immediate availability of RF and mixed-mode foundry design kits (FDKs) for UMC's 0.18-micron process technology. The companies say the FDKs are a result of a three-way collaboration. Giga Solution has integrated its RF silicon measurement result and component library into Mentor's EDA flow for SoC designs. The component library includes scalable models with layout. Magma Design Automation Inc. announced that it has validated its design flow and is among the first "solution providers" to be awarded IBM's "Ready For IBM Technology" mark for IBM's 0.13-micron process technologies. The companies says that common customers have used the Magma-IBM design flow to tape out chips from 8 million gates to 12 million gates, and that three more designs are preparing to tape out with IBM's 0.13-micron and 0.18-micron CMOS technologies. Magma has qualified libraries and technology files for IBM's 0.13-micron CMOS technologies and has integrated them into Magma's RTL-to-GDSII system. MIPS Technologies, Inc. announced that Metalink has licensed the MIPS32 M4K core and the MIPS32 4KEc core with CorExtend capabilities. MIPS says that by incorporating these 32-bit cores into its broadband applications, Metalink further builds on its portfolio of MIPS-based products for the telecommunications market. Metalink will use the M4K and 4KEc cores, as it has done with the 4Km core, in combination with its universal software programming interfaces. The Olympus-DSL unified platform supports various industry standards including VDSL, SHDSL, HDSL2, HDSL4, SDSL, and HDSL. Also from MIPS - The company announced that ADMtek Inc. has successfully taped out a MIPS-based SoC design targeted to the worldwide home gateway market. The company says the announcement was made by ADMtek's CEO at an event celebrating MIPS Technologies' 1-year anniversary of entering the Taiwan marketplace. The MIPS-based chip, implemented in a 0.18-micron process by Chartered Semiconductor, integrates a MIPS32 4Kc core with a six-port switch engine, PHY, USB 1.1 host, and a PCI bridge. Also from MIPS - The company announced that it has entered into an agreement with Socle Technology Corp. to facilitate the design of MIPS-based SoCs by fabless and system companies though various design services offered by Socle. Under the terms of the agreement, Socle has taken a license for the MIPS32 4KE and 4K family of cores. Socle announced it has completed a tape-out for a MIPS licensee using Socle's deep-submicron "SoC-ImP" design flow. The announcement was also made at the event celebrating MIPS Technologies' 1-year anniversary of entering the Taiwan marketplace. Nassda Corp. announced that Intersil Corp. has selected Nassda's HSIM simulator and analysis tool for the design and verification of complex mixed-signal circuit blocks used in Intersil"s PRISM wireless LAN ICs. Under a multi-license agreement, Intersil PRISM chip-set designers will use Nassda's HSIM circuit simulator to perform transistor-level analysis. Intersil is using HSIM's integration with the Cadence analog design environment. Real Intent has released a new version of the company's flagship product, Verix 4.0, to provide what the company says is "multi-million gate capacity for formal assertion verification." Verix, first introduced in 2000, is an assertion-driven formal verification system for determining that a design is free from a large class of errors. The system includes 14+ classes of automatic assertions, as well as a Verilog/VHDL like assertion language that allows users to define their own design assertions. Verix 4.0 can process a multi-million gate design without user partitioning and, based on major performance upgrades, can prove assertions that are 10x to 20x more complex than the previous versions. TelASIC Communications announced that it used Sequence Design's Columbus-RF for extraction technology to handle resistance, capacitance, and inductance in coordination with the IBM SiGe design kits. Don Devendorf, TelASIC CTO said the Sequence tool is important because, "It is essential to have RLC extraction when working with SiGe because of the high speeds achieved." TelASIC's design flow is based on Cadence's Analog Artist and Spectre RF simulator. Tenison EDA announced that Seaway Networks has adopted VTOC, the Tenison Verilog/VHDL to C/C++ modeling tool. Tenison VTOC creates fast cycle-accurate hardware models in C, C++, or SystemC. Mustafa Hamid, Software Manager at Seaway Networks, said: "We used VTOC to create a C model from the RTL of our Network Content Processor, a multi-million gate design. The C model allowed us to easily add new points of visibility into the hardware and it runs about 10 times faster than the compiled Verilog. The C model is also easier to integrate with the rest of the software for initial testing." Coming soon to a theater near you The Semico Impact Conference Series - Taking place on April 29th at the Silicon Valley Conference Center in San Jose, CA, conference organizers say the all-day event will "feature the power of Semico's accurate and insightful forecasts combined with cutting edge perspectives from the industry insiders who are propelling our industry forward." The topic for the day is "90 nanometer and Beyond!" and the agenda will include discussion of tools for meeting time-to-market schedules along with increased yields and profitability, the move to advanced technologies in SoC, FPGA, ASIC products, and strategies for streamlining the test, verification, and prototyping of designs. In other words, the CMP Media sponsored event will have something for just about everyone. ( www.semico.com/impact/welcome.htm ) Newsmakers Hier Design Inc. has named Dino Caporossi as Vice President of Marketing. He will report to Jackson Kreiter, CEO and chairman, and will be responsible for product and technical marketing, PR, and marketing communications. Previously, Caporossi was Vice President of Corporate Marketing at Verplex Systems, Inc. Prior to joining Verplex, he held marketing management positions at Cadence Design Systems, Compass Design Automation, and Valid Logic. Caporossi has 20 years' experience in EDA marketing and electronics design. He has an MSEE from Johns Hopkins University and a BSEE from the University of Maryland. Nassda Corp. announced that the company has been named No. 2 on Electronics Business' list of 30 best small electronics companies. Companies were ranked by annual revenue growth from 2000 to 2002. The Reed Research Group of Electronics Business says it picked the 30 best small companies by "compiling a list of more than 200 public electronics companies with annual revenues less that $250 million that had shown strong annual and quarterly revenue growth, and a short list of noteworthy private companies." Open Core Protocol International Partnership (OCP-IP) announced that Amphion Semiconductor, Inc. is joining the organization. OCP-IP says that membership in the organization will allow Amphion's customers to "optimize design resources, and shorten design cycles, lower design costs, and bring products to market faster." Good stuff. Silicon Valley Profiles - This info was forwarded from several sources this past week and is worth a second look, given time and interest in the people that shaped the history of the place. "For the past few years, Rob Walker has been interviewing many of those responsible for making Silicon Valley what it is today. There are 25 interviews, including Gordon Moore, Jerry Sanders, Jack Gifford, Arthur Rock, Gil Amelio, Harry Sello, Charlie Spork and the list goes on. These interviews are in video form and can be found at the Stanford website below. Each interview takes an hour or so, and are full of interesting stories, history and tidbits of Valley lore. Fortunately, Stanford is archiving these interviews so they will be available to future generations, historians and researchers, giving the human side of the technical revolution. You may already be aware of these interviews, but in case you didn't I thought you would find them interesting and also full of memories. Enjoy. Signed, Geri Hadley" ( silicongenesis.stanford.edu/complete_listing.html ) Virtual Silicon Technology, Inc. has named Dan Hillman as Vice President, Business Operations and Infrastructure. Hillman will be responsible for applications engineering, customer support, EDA tools and methodology, IP development methodology and productization. Hillman has 25+ years' experience in chip engineering, high-tech development and management. Previously, he was Vice President of Engineering at inSilicon, Corporate Applications Group Director for Synopsys' Physical Synthesis Business Unit, and spent 11 years at Apple Computer directly involved in the design of the Apple IIGS, Macintosh, and Newton. Hillman began his career at RCA and Zilog corporations, and has a BSEE from Purdue University. The VSI Alliance (VSIA) announced the merger of the activities of the Implementation/Verification (I/V), Analog Mixed-Signal (AMS), and Signal Integrity (SI) development working groups (DWGs) into the new Implementation DWG. Raminderpal Singh, Senior Engineering Manager for the IBM Microelectronics Division and previously the co-chairman of the AMS DWG has been elected to the position of Chairman of the Implementation DWG. VSIA says that Singh will spearhead the plan to develop a more streamlined, cohesive approach to developing physical implementation guidelines for IP providers. ( www.vsi.org ) Yamacraw, the Georgia state economic development initiative, announced that a division of Agilent Technologies, Agilent EEsof EDA, has joined as a full member. Through its membership, Yamacraw says Agilent will provide software and hardware to help create "state-of-the-art electronic capabilities" in Georgia's research universities. Agilent says that it will benefit from its investment by "ensuring that Georgia's university students are trained and experienced on their tools and technology." Also from Agilent - The company announced the availability of the Agilent EEsof Knowledge Center, a web-based site for engineers who need EDA technical information and support tools. The company says the EEsof Knowledge Center will help engineers take advantage of EDA design tools and "improve productivity by providing easy access to technical documents, support examples, software downloads, and discussion forums." The center is available on-line, 24 x7. Users can browse through approximately 4,000 support documents and 400 support examples written by Agilent technical support engineers, with examples ranging from simple applications to advanced design problems. In the category of On deadline No matter which way you cut it, the last 7 days have been beyond description - from thundering headlines out of Iraq to a strategic acquisition in EDA as discussed above. As I have said before, this is not the forum for discussions of war and peace. However, it has been difficult for many of us to concentrate on business and personal issues as international news has been breaking non-stop, night and day, particularly in this last week. But, as we all know, neither business nor personal issues will wait. In this past 7 days, our oldest kid settled on a graduate school, the culmination of a decision-making process which included trips to four universities in 4 weeks. I was traveling companion on the last of those trips and hope to write about my visit to the University of Michigan in next week's newsletter. Meanwhile, in these same past 7 days, our youngest has settled on a college and we moved an elderly parent out of her home of 48 years and into assisted living. In order to keep up with this newsletter and the industry this week, I've been talking to PR folks and company executives from the phone in the kitchen of my mother-in-law's home, surrounded by packing boxes, bubble wrap, and the mountainous miscellaneous piles that accumulate during a move. Our own house is now awash with literature from graduate schools, letters from undergraduate schools, a dozen extra lamps, 100s of additional books and boxes, and forwarded mail from a just-vacated home. Finally, in the last 7 days, I moderated a panel at an all-day FSA forum (Fabless Semiconductor Association) where folks from MIPS, PMC-Sierra, and Cadence discuseed a broad range of issues related to Design-to-Silicon. That panel discussion will also be highlighted in this newsletter in the next several weeks. But right now, this newsletter is late. It's Friday afternoon and the Web Master is awaiting copy. From international news, to EDA news, to family matters - this week has not been kind to those who need contemplative time to produce readable copy. Hopefully, next week will be better. --Peggy Aycinena is a Contributing Editor and can be reached at peggy@ibsystems.com . You are subscribed as: [dolinsky@gsu.by]. EDAWeekly is a service for EDA professionals. EDAToolsCafe respects your online time and Internet privacy. If you would prefer not to receive this type of email or if you consider this message as unsolicited commercial e-mail, please click here . PLEASE NOTE: You can change the frequency of this newsletter by clicking here . If you have questions about EDAToolsCafe services, please send email to edaadmin@ibsystems.com . Copyright c 2002. Internet Business Systems, Inc. All rights reserved.